Video conferencing interface

ABSTRACT

A video conferencing circuit ( 12 ) is configured to receive an input ( 26 ) from one of a plurality of video input devices. The video signal is then stored, compressed and transmitted by an interface circuit such as a modem ( 18 ). Video signals from a remote location are received from the modem ( 18 ), decompressed, stored and then transferred for display on one of a plurality of video output devices.

This application claims the benefit of U.S. Provisional Application No.60/094,646, filed 30 Jul. 1998.

TECHNICAL FIELD

This invention relates to video conferencing systems and, morespecifically, to a system which interfaces with one or more of aplurality of video input and one or more of a plurality of outputdevices.

BACKGROUND

Video conferencing systems are typically designed for use with oneparticular type of video input device, such as an NTSC camera (“NTSC”means the North American and Japanese analog video standard), a PALcamera (“PAL” means the European analog video standard), a digitalcamera, or a high speed serial interface camera (e.g., a FireWire orUniversal Serial Bus (USB) camera). Such systems are also typicallydesigned for use with one particular output device, such as an NTSC orPAL video monitor, a television set, a Liquid Crystal Display (LCD)screen, or a computer monitor.

Systems having an interface for video conferencing systems that allowthe users or manufacturers of such systems to intermingle video inputand output devices as they choose, or as a particular video conferencingapplication dictates, rather than being required are not known. That is,existing systems are believed to require a particular video input deviceand a particular output device dictated by the video signal formal forthe selected video conferencing system.

DISCLOSURE OF INVENTION

A video conferencing interface is part of a standards-based videoconferencing system with excellent video and audio quality, highcompression, and great flexibility, all at a low cost. The interfaceincludes an Application Specific Integrated Circuit (ASIC) thatincorporates a unique blend of computation and data path designsimplemented in hardware, as well as processing and control developed forflexibility using a standard processor.

The “hybrid” method of computation and control available in thedisclosed system provides an advantage over “single solution”counterparts in which computation and control is implemented indedicated hardware only. The use of dedicated hardware only leads torelative inflexibility in bit rate control. The “hybrid” method ofcomputation and control in the disclosed system provides and anadvantage over counterparts that use a software-programmed processoronly, thereby abandoning the speed advantages of a hardwareimplementation.

The disclosed system employs hardware to implement or provide forcomputation and for a data path to provide for high speed dataprocessing at a much faster rate than could be done in a processor-onlyenvironment (i.e., software). A standard software based processor allowsfor flexibility of control so the system can be made adaptable forseveral different configurations. However, the result is a slower speedbecause of the software configuration. To attain higher speeds usinghardware, a separate hardware configuration would be needed for eachvariation needed leading to considerable cost and complexities forimplementation.

For example, it is often desirable to control the bit rate at which thesystem interface processes images so an appropriate balance can bestruck between the quality of the images processed, on the one hand, andthe speed with which images are processed, on the other hand. When rapidmotion occurs in the processed images, for example, it is typicallydesirable to operate at an increased bit rate so that the rapid motionis quickly processed and communicated. However, the high speedprocessing negatively impacts image quality. When the images to beprocessed are relatively static from image to image (e.g., frame toframe), it typically is desirable to operate at a reduced bit rate, butwith increased image quality. In a hardware-only implementation, suchflexibility would have to be hardwired at greater expense, or wouldsimply be unavailable. In a software-only implementation, flexibility ismaintained, but at the expense of reduced processing speed. The presentinvention employs a “hybrid” approach, heretofore unknown, to secure thebenefits of a fixed hardware and a fixed software solution.

In the described embodiment of the present invention, the ASIC is thekey to implementing this hybrid approach. The ASIC provides a hardwiredimplementation for computation and data movement while also providingthe flexibility inherent in processor-based processing and control.

In addition to the ASIC, the system incorporates a memory to store thevideo information as it is being compressed and/or displayed. The systemalso includes memory and Electrically Erasable Programmable Read OnlyMemory (EEPROM) for instructions and data storage for the processor,audio input and output, and a MOdulator/DEModulator (MODEM) fortelephone/network interface. (The EEPROM and MODEM are actually optionaldepending on the configuration requirements.)

The ASIC also includes several interfaces that are flexible in theirfunction that allow for several different system configurations withminimal modification or cost impact. These interfaces include the videoinput, the video output, and the high speed serial interface.

BRIEF DESCRIPTION OF DRAWINGS

In the drawings:

FIG. 1 is a block diagram depiction of a basic ASIC of the prior artsuitable for use in processing video signals;

FIG. 2 is a block diagram of the ASIC suitable for use in one form of avideo system of the present invention;

FIG. 3 is is a block diagram of the ASIC suitable for use in anotherform of a video system of the present invention;

FIG. 4 is a block diagram of a high speed serial interface circuit foruse with a video system of the present invention;

FIG. 5 is a block diagram of a video input block of an ASIC used with avideo system of the present invention;

FIG. 6 is a block diagram of a bus control block of an ASIC used with avideo system of the present invention; and

FIG. 7 is a block diagram of a video output block of an ASIC used with avideo system of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

As shown in FIG. 1, a conventional ASIC 10 may be included on a circuitboard 12. The circuit board 12 includes a memory 14 connected to aMemory Control 30 forming a memory module 15 that functions to retainvideo signals. Memory 14 may be implemented as a dynamic random accessmemory (DRAM), a static random access memory (SCRAM), or other suitablememory device architecture known by persons skilled in the art.

The circuit board 12 may also have an optional EEPROM module 16. Aseparate processor memory module 18 (e.g., SCRAM DRAM, etc.) along withan audio input/output (I/O) module 20 (connected, for example, to amicrophone or speaker), and a MODEM and/or Network interface (e.g., LANor local area network interface) module 22 which together function as aremote video interface circuit 19 may also be included on the circuitboard 12.

In one operational configuration, Video-In circuitry 24 receives digitalvideo signals 26 from a single or selected video signal source. “H.263”is a video compression/decompression standard established by theInternational Telecommunications Union (ITU). H.263 Encode circuitry 34directs the Memory Control circuitry 30 to forward stored digital videodata sent to it from the video memory module 15. The Memory Controlcircuitry 30 sends the stored video data that it receives out onto andalong the memory bus 32. As the H.263 Encode circuitry 34 encodes (i.e.,compresses) the stored digital video data, it passes the now encodeddigital video data to a MODEM or a Network module 22 for transmission toa remote station (not shown) at which location the digital video datamay be decoded and subsequently displayed for viewing by a user. Theremote station may include the inventive video conferencing interfacedescribed herein, or it may be a conventional video conferencing systeminterface.

Encoded digital video data is transmitted by and also received from theremote station or another station through the MODEM or the Network 22.The MODEM or the Network 22 transmit and receive data. If a MODEM isused, the signal is modulated and or demodulated and transmitted over anappropriate line such a telephone line or any equivalent thereof.Alternately, it may be transmitted through a network wiring arrangementwhich is configured to provide video signal transmission.

The data received from the remote location through a MODEM, a network orwhat ever else may be extant, is transferred through the Processorcircuitry 40 to the Bus Control circuitry 36. The Bus Control Circuitry36 passes the data over the data bus 38 to H.263 Decode circuitry 42 fordecoding. After decoding the digital video data, the H.263 Decodecircuitry 42 forwards the decoded digital video data to the MemoryControl circuitry 30 over the memory bus 32 for storage in the DRAM 14.Video Out circuitry 44 then directs the Memory Control circuitry 30 toretrieve the stored digital video data from the DRAM 14 for output bythe Video Out circuitry 44 in digital form for display by a selectedvideo display device (not shown) connected to receive the video signalfrom the Video Out Circuitry 44.

Alternatively, serial digital video data, or serial control signals froman attached computer system, can be input or output through high speedserial interface circuitry 46, as will be described in more detailbelow.

Support circuitry 48 and performs certain “housekeeping” and controlfunctions. The Support circuitry 48 interacts with the EEPROM module 16via a well-known I²C bus 50, handling interrupt signals, INT, and resetsignals, RST, and programming an array of programmable I/O pins, PIO(not shown).

The EEPROM module 16 may be used to store machine code for the operationof the Processor circuitry 40. At start-up, the machine code can betransferred from the relatively slow EEPROM module 16 to the relativelyfast processor memory device 18 for use by the Processor circuitry 40during normal operations.

The system of the present invention shown in FIG. 2 incorporates aplurality of video input options supplied by video input means 11 theoutput of which is supplied as the input video signal 26. The inputmeans 11 is here shown to include two or more sources of video signals.The sources illustrated include an Internal Digital Camera 52, anInternal NTSC or PAL video camera 56, an External NTSC or PAL videoCamera 58. Input may also be had from an External High Speed SerialCamera 60. Although shown separated from the input means 11, the HighSpeed Serial Camera 60 can be incorporated into the input means 11 orpositioned separately to supply an input signal to the data bus 38.

An “internal” camera 52 is a camera in which the lens and interfacecontrol are mounted inside the system enclosure, while an “external”camera interfaces through a connector which may be the video decoder 54.

More specifically, as shown in FIG. 2, the digital video signals 26 canbe generated by the internal digital camera 52, or by the Video Decodermodule 54 converting analog NTSC or PAL signals from the internal NTSCor PAL camera 56 or the external NTSC or PAL camera 58 to the digitalvideo signals 26. Alternatively, or in addition, a digital camera 60having a high speed serial output, such as a FireWire or USB port, canoutput serial digital video signals to the high speed serial interface46 for further processing and transmission to the data bus 38.

The ASIC 10 of FIG. 2 is configured to have a memory means 15 thatincludes the DRAM 14 and the memory control 30. Memory control circuitry30 transfers the digital video signals 26 from a memory bus 32 to theDRAM 14 for storage and also to the H.263 encode module 34 forcompression prior to processing by the video processing means 35. Thevideo processing means 35 includes the Processor 40 as well as thesupport circuit 48 and the bus control 36. It also includes theprocessor Memory 18 and the EEPROM 16 if provided.

The video processing means 35 and more specifically the Processorcircuitry 40 directs the encoded digital video data to the remoteinterface circuit 19. The remote interface circuit 19 is any suitablecircuit to transmit and receive video conferencing signals to and from aremote source. That is, the remote interface circuit 19 is configured toreceive video signals and preferably voice signals from a remote sourceto effect what may be referred to as video conferencing. The outgoingvideo signals as well as audio signals are sent to a remote locationwhich ideally is returning similar video signals and audio signals forprocessing by the ASIC and for presentation as a video signal on aselected video display or output device. The remote interface means 19is here illustrated to include the MODEM 22 and Audio circuit 20.

The ASIC 10 of FIG. 2 has all the other processing circuitry of FIG. 1as shown in FIG. 2 while at the same time differing significantly inthat a plurality of video input arrangements can be accepted from thevideo input means 11 using a combination of software and hardware tofacilitate speed in processing and flexibility.

The system of the present invention in another embodiment depicted inFIG. 3 may also integrate one of several video output options, includingNTSC/PAL 68, a Video Modulator 62, LCD 72, RGB 71, and a remote deviceconnected by conductors 73 through the High Speed Serial Interface 46.

More specifically, as shown in FIG. 3, the digital video output of theVideo Out circuitry 44 can be provided to video output means 43 which ishere shown to include a Video Modulator module 62 to convert the digitalvideo output from the video out circuitry 44 to a modulated analogsignal 64. The analog signal is then multiplexed by a Cable Multiplexermodule 66 for output as a TV channel (e.g., channel “3”) to a monitor68. Alternatively, the digital video output of the Video Out circuitry44 can be converted by a Video Encoder module 70 to an NTSC or PALanalog format suitable for input to a dedicated port on the monitor 68,or can be converted into an LCD format signal for an LCD screen 72. Instill another alternative, the Video Encoder module 70 can convert thedigital video output from the Video Out circuitry 44 to an RGB signal 71suitable for direct application to a computer monitor (not shown).

The system of the present invention can be configured or modifiedthrough the specific use of the High Speed Serial Interface 46 connectedto separate video 47 not illustrated in FIG. 3. The video means 47 (FIG.4), can be used for video input, and/or video output. Additionally, itcan be used to connect the system as a peripheral or remote device toanother controller. This controller could be, for example, a cable box,a set top box, a personal computer, or any number of general purpose ortask specific controller devices. Likewise, this also allows the systemto easily be integrated directly into a stand-alone teleconferencingdevice or video phone.

More specifically, as shown in FIG. 4, the depicted ASIC 10 has a HighSpeed Serial Interface circuit 46 (e.g., a FireWire or USB port) whichoutputs serial digital video data 71 to video means 47. The video means47 may include a controller with modem 74, which then interfaces withthe telephone system 76 or a separate monitor such as monitor 68.

As shown in FIG. 5, the Video-In circuitry 24 includes InputConfiguration circuitry 78 that receives digital video signals 26, aswell as serial digital video data from the data bus 38. Control registercircuitry 80 set by the Bus Control circuitry 36 (see FIG. 2) causes theInput Configuration circuitry 78 to select and output either the signals26 or the data from the data bus 38 in a 4:2:2 YUV format. PixelDecimation circuitry 82 then reduces the “color” component of the outputsignal, thereby reducing the data density of the signal, by outputtingthe signal in a 4:1:1 YUV format. Then, a First-In-First-Out (FIFO)buffer 84 holds the output signal before transferring it to the memorymeans 15 via memory bus 32.

As shown in FIG. 6, the Bus Control circuitry 36 includes Bone Interfacecircuitry 86 for receiving data from the data bus 38 (otherwise known asthe “backbone”) and Processor Interface circuitry 88 which communicateswith the Processor circuitry 40 (see FIG. 4). Arbitration and Controlcircuitry 90 selects which Interface circuitry 86 and 88 will be activeat any one time, and Host Interface circuitry 92 communicates datainternally to and from the selected Interface circuitry 86 or 88. Datafrom the Host Interface circuitry 92 proceeds to Data Interface Controlcircuitry 94, while register information proceeds to Register InterfaceControl circuitry 96. Both of the circuitry 94 and 96 communicate withThird Party Module circuitry 98, such as FireWire or USBserial-to-parallel circuitry.

As shown in FIG. 7, the Video Out circuitry 44 includes MemoryControl/Sequencer circuitry 100 that directs the Memory Controlcircuitry 30 (see FIG. 1) to provide it with digital video data from theVideo Memory module 14 (see FIG. 1) in the proper sequence. Line Storecircuitry 102 then acts as a buffer for storing the video data until twovideo lines of data are stored. Interpolator circuitry 104 then reversesthe actions of the Pixel Decimation circuitry 82 (see FIG. 5) byinterpolating between each two lines of video data it receives togenerate a 4:2:2 YUV signal. A storage FIFO buffer 106 then stores theinterpolated video data, and Control Registers circuitry 108 controlledby the Bus Control circuitry 36 (see FIG. 1) then causes Encoder Controlcircuitry 110 to output the stored video data, or not, as the situationmay dictate. At the same time, the stored video data is provided on thedata bus 38 to the Bus Control circuitry 36 (FIG. 1) for use by the HighSpeed Serial Interface circuitry 46 (see FIG. 1).

The systems of FIG. 2 or 3 can be easily and inexpensively configured asseveral different devices including, but not limited to: a PC peripheralfor camera or video conferencing; a cable box peripheral for camera orvideo conferencing; and a remote camera for surveillance systems. Inaddition, the system that includes the circuit of FIG. 2 or 3 can beintegrated into or tightly coupled with other hardware to create otherdevices including, but not limited to, a set top box video conferencingsystem; a cable box video conferencing system; and a video phone.

It should be understood, of course, that the systems depicted in FIGS.2–7 may be a transmitting or receiving station, or, more likely in mostvideo conferencing systems, both.

The embodiments herein illustrated and described are not intended tolimit the scope of the invention as defined in the following claims.

1. A video conferencing circuit for use with a plurality of video inputdevices and a video output device, said video conferencing circuitcomprising: video input means configured to select an input video signalfrom one of a plurality of video signal generating devices, said videoinput means including a video decoder circuit to receive selected videosignals and convert said selected video signals to an input videosignal; a remote interface circuit; a video output device; and anapplication specific integrated circuit (ASIC) connected to said videoinput means, to said video output device and to said remote interfacecircuit, said ASIC having: a high speed serial video input, a video-incircuit connected to said video input means to receive one of said inputvideo signal from one of said plurality of video signal generatingdevices and said high speed serial video input, said video-in circuitincluding an input configuration circuit connected to receive one of aplurality of video input signals and a high speed serial video input, acontrol register connected to said video processing means to receivecontrol signals therefrom and said input configuration circuit to supplyinput control signals to cause said input configuration circuit tooperate to supply said one of said plurality of video input signals assaid input video signal to said memory circuit, a memory circuitconnected to said video-in circuit to receive said one of said inputvideo signal and said high speed serial video input, said memory circuitbeing configured to retain and transmit said one of said input videosignal and said high speed serial video input as stored data, datacompression means connected to said memory circuit to receive saidstored data and to compress said stored data through an encoding processto form outgoing compressed data, video processing means connected toreceive said outgoing compressed data and connected to said remoteinterface circuit to transmit said outgoing compressed data and toreceive incoming compressed data from a remote station, said videoprocessing means also being connected to said video-in circuit, saidmemory circuit, said video decompression means, said video receivingmeans, and to said video image out means to control the flow of videosignals thereinbetween, video decompression means connected to saidvideo processing means to receive said incoming compressed data andconfigured to decompress and to transmit said incoming compressed datato said memory circuit, said memory circuit being configured to convertsaid incoming compressed data to incoming stored data, and video imageout means connected to receive incoming stored data from said memorycircuit and to transmit said incoming stored data as a video imagesignal to a video display device; wherein said memory circuit includes amemory structure and a memory control circuit to convert said one ofsaid input video signal and said high speed serial video input to storeddata and to convert said incoming compressed data to incoming storeddata and wherein said output of said input configuration circuit issupplied to a decimation circuit which operates to reduce the density ofthe said output signal and is connected to a buffer to store andtransmit an output which is a video.
 2. The video conferencing circuitof claim 1 wherein said remote interface circuit includes a modem. 3.The video conferencing circuit of claim 1 wherein said memory structureis a DRAM configured to receive and store said stored data and saidincoming stored data.
 4. The video conferencing circuit of claim 1further including a data bus interconnected between said video-incircuit, said memory circuit, said encoding circuit, said decodingcircuit and said video out circuit for transmitting control signalstherebetween, and wherein said video processing means includes a buscontrol circuit connected to said data bus to supply said controlsignals thereto.
 5. The video conferencing circuit of claim 4 whereinsaid bus control circuit includes a backbone interface circuit connectedto said data bus, said backbone interface circuit being configured togenerate and to supply said control signals to said data bus.
 6. Thevideo conferencing circuit of claim 5 wherein said video processingmeans includes a data processor connected to said remote interfacecircuit, a processor interface connected to said data processor tosupply data thereto and a arbitration and control circuit connected tosaid processor interface and to said backbone interface circuit andconfigured to select and activate one of the backbone interface circuitand the processor interface, and a host interface circuit connected tosaid arbitration and control circuit, said host interface circuit beingconfigured to supply to and receive data from the processor interfaceand the backbone interface circuit, said arbitration and control circuitalso being connected to supply and receive video signals to and from anexternal device for obtaining and displaying video images.
 7. A videoconferencing circuit for use with a plurality of video output devicesand a video input device, said video conferencing circuit comprising:video output means configured to select one of a plurality of videooutput devices to receive an output video signal; a remote interfacecircuit; a video input device; and an application specific integratedcircuit (ASIC) connected to said video input device, to said videooutput means and to said remote interface circuit, said ASIC having: ahigh speed serial video inputs a video-in circuit connected to saidvideo input device to receive one of a video input signal from saidvideo input device and said high speed serial video input, a memorycircuit connected to said video-in circuit to receive said one of saidvideo input signal and said high speed serial video input, said memorycircuit being configured to retain and transmit said one of said videoinput signal and said high speed serial video input as stored data, datacompression means connected to said memory circuit to receive saidstored data and to compress said stored data through an encoding processto form outgoing compressed data, video processing means connected toreceive said outgoing compressed data and connected to said remoteinterface circuit to transmit said outgoing compressed data and toreceive incoming compressed data from a remote station, videodecompression means connected to said video processing means to receivesaid incoming compressed data and configured to decompress and totransmit said incoming compressed data to said memory circuit, saidmemory circuit being configured to convert said incoming compressed datato incoming stored data, said video processing means also beingconnected to said video-in circuit, said memory circuit, said videodecompression means, said video receiving means, and to said video imageout means to control the flow of video signals thereinbetween, and videoimage out circuit connected to receive incoming stored data from saidmemory circuit and to transmit said incoming stored data as a videoimage signal to said one of said plurality of video output devices ofsaid video output means; wherein said memory circuit includes a memorystructure and a memory control circuit to convert said one of said videoinput signals and said high speed serial video input to stored data andto convert said incoming compressed data to incoming stored data;wherein said video-in circuit includes an input configuration circuitconnected to receive said video input signal and said high speed serialvideo input, a control register connected to said video processing meansto receive control signals therefrom and said input configurationcircuit to supply input control signals to cause said inputconfiguration circuit to operate to supply said one of said video inputsignal and said high speed serial video input to said memory circuit;and wherein said output of said input configuration circuit is suppliedto a decimation circuit which operates to reduce the density of the saidoutput signal and is connected to a buffer to store and transmit anoutput which is a video.
 8. The video conferencing circuit of claim 7wherein said remote interface circuit includes a modem.
 9. The videoconferencing circuit of claim 7 wherein said memory structure is a DRAMconfigured to receive and store said stored data and said incomingstored data.
 10. The video conferencing circuit of claim 7 furtherincluding a data bus interconnected between said video-in circuit, saidmemory circuit, said encoding circuit, said decoding circuit and saidvideo out circuit for transmitting control signals therebetween, andwherein said video processing means includes a bus control circuitconnected to said data bus to supply said control signals thereto. 11.The video conferencing circuit of claim 10 wherein said bus controlcircuit includes a backbone interface circuit connected to said databus, said backbone interface circuit being configured to generate and tosupply said control signals to said data bus.
 12. The video conferencingcircuit of claim 11 wherein said video processing means includes a dataprocessor connected to said remote interface circuit, a processorinterface connected to said data processor to supply data thereto and aarbitration and control circuit connected to said processor interfaceand to said backbone interface circuit and configured to select andactivate one of the backbone interface circuit and the processorinterface, and a host interface circuit connected to said arbitrationand control circuit, said host interface circuit being configured tosupply to and receive data from the processor interface and the backboneinterface circuit.
 13. A video conferencing circuit for use with aplurality of video output devices and a video input device, said videoconferencing circuit comprising: video output means configured to selectone of a plurality of video output devices to receive an output videosignal; a remote interface circuit; a video input device; and anapplication specific integrated circuit (ASIC) connected to said videoinput device, to said video output means and to said remote interfacecircuit, said ASIC having: a high speed serial video input, a video-incircuit connected to said video input device to receive one of a videoinput signal from said video input device and said high speed serialvideo input, a memory circuit connected to said video-in circuit toreceive said one of said video input signal and said high speed serialvideo input, said memory circuit being configured to retain and transmitsaid one of said video input signal and said high speed serial videoinput as stored data, data compression means connected to said memorycircuit to receive said stored data and to compress said stored datathrough an encoding process to form outgoing compressed data, videoprocessing means connected to receive said outgoing compressed data andconnected to said remote interface circuit to transmit said outgoingcompressed data and to receive incoming compressed data from a remotestation, video decompression means connected to said video processingmeans to receive said incoming compressed data and configured todecompress and to transmit said incoming compressed data to said memorycircuit, said memory circuit being configured to convert said incomingcompressed data to incoming stored data, said video processing meansalso being connected to said video-in circuit, said memory circuit, saidvideo decompression means, said video receiving means, and to said videoimage out means to control the flow of video signals thereinbetween,video image out circuit connected to receive incoming stored data fromsaid memory circuit and to transmit said income to transmit saidincoming stored data as a video image signal to said one of saidplurality of video output devices of said video output means, a memorycontrol sequencer connected to said memory circuit, said memory controlsequencer being configured to generate and send to the memory circuitinstructions to cause the supply said memory circuit to supply saidmemory control sequencer with said incoming stored data and said memorycontrol sequencer being configured to supply said incoming stored dataas an output, a line buffer connected to receive said incoming storeddata from said memory control sequencer, said line buffer beingconfigured to store a video line of said incoming stored data as firstvideo out signal and another video line of said stored video data as asecond video out signal, an interpolator circuit connected to said linebuffer to receive said first video out signal and said second video outsignal and to generate an interpolated video signal, a buffer connectedto said interpolator circuit to receive said interpolated video signaltherefrom, a control register connected to said data bus to receivecontrol signals from said video processing control and to said buffer tosupply signals to cause said buffer to supply said interpolated videosignal, and an encoder connected to said buffer to receive saidinterpolated video signal therefrom and to said control register toreceive signals to cause said interpolated video signal to be suppliedas the video image signal to one of said plurality of video outputdevices of said video output means, wherein said memory circuit includesa memory structure and a memory control circuit to convert said one ofsaid video input signals and said high speed serial video input tostored data and to convert said incoming compressed data to incomingstored data.